Testing in the Fourth Dimension - Auburn University
Lecture Lecture 4 4 Yield Yield Analysis Analysis and and Product Product Quality Quality Yield and manufacturing cost Clustered defect yield formula Defect level Test data analysis Example: SEMATECH chip Summary Copyright 2001, Agraw
al & Bushnell VLSI Test: Lecture 4 1 VLSI VLSI Chip Chip Yield Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is
denoted by symbol Y. Cost of a chip: Cost of fabricating and testing a wafer Yield Number of chip sites on the wafer Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 2 Clustered Clustered VLSI VLSI Defects Defects Good chips Faulty chips Defects Wafer Unclustered defects Wafer yield = 12/22 = 0.55
Copyright 2001, Agraw al & Bushnell Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 VLSI Test: Lecture 4 3 Yield Yield Parameters Parameters Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter () Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x ) (a+x ) (Ad /) x = . x ! (a) (1+Ad /) +x where is the gamma function = 0, p (x ) is a delta function (maximum clustering) = , p (x ) is Poisson distribution (no clustering) Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 4 Yield Yield Equation Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / ) - Example: Ad = 1.0, = 0.5, Y = 0.58
Unclustered defects: = , Y = e - Ad Example: Ad = 1.0, = , Y = 0.37 too pessimistic ! Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 5 Defect Defect Level Level or or Reject Reject Ratio Ratio
Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 6 Determination Determination of of DL DL
From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL. Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 7 Modified Modified Yield Yield Equation Equation
Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, Stuck-at fault coverage, T The modified yield equation: Y (T ) = (1 + TAf / ) Assuming that tests with 100% fault coverage (T = 1.0) remove all faulty chips, Y = Y (1) = (1 + Af / ) Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 8 Defect Defect Level Level Y (T ) - Y (1) DL (T ) = Y (T )
( + TAf ) = 1 - ( + Af ) Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, is the fault clustering parameter. Af and are determined by test data analysis. Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 9 Example: Example: SEMATECH SEMATECH Chip Chip
Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.8 CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM) Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 10 Stuck-at fault coverage
Test Test Coverage Coverage from from Fault Fault Simulator Simulator Vector number Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 11 Measured chip fallout Measured Measured Chip Chip Fallout Fallout
Vector number Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 12 Chip fallout and computed 1 -Y (T ) Model Model Fitting Fitting Chip fallout vs. fault coverage Y (1) = 0.7623 Measured chip fallout Y (T ) for Af = 2.1 and = 0.083 Stuck-at fault coverage, T Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4
VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (). Yield drops as chip area increases; low yield means high cost. Fault coverage measures the test quality. Defect level (DL) or reject ratio is a measure of chip quality. DL can be determined by an analysis of test data. For high quality: DL < 500 ppm, fault coverage ~ 99% Copyright 2001, Agraw al & Bushnell VLSI Test: Lecture 4 15
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