Fast pulsed power supply for ILC damping ring kicker Jinhui Chen Accelerator Research Center , IHEP ,CAS , China International Workshop on Accelerator R&D for USR Huairou, Beijing from Oct. 30 to Nov. 1, 2012 1 International Linear Collider(ILC) ILC is a high luminosity linear collider at ECM=500GeV, which consists of: two 11 km long main linacs; a 5GeV electron and positron damping ri ngs with C=6.7km; a 4.5 km long beam delivery system. a polarized electron source; an undulator-based positron source; beam transport line and bunch compresso r system;

2 ILC damping ring(DR) ILC damping rings is designed mainly to damp the incoming beam emittance and jitter to low level and provide highly stable beams for downstream systems. 6.7 km, 5 GeV Damping Ring 3 ILC DR injection and extraction The length of the bunch train from the ILC injector is very long, about 300k m. If bunch train was injected into DR without compressed, the DR should be very huge. To control the cost, the bunch train compression and decompression are necessary. So, the beam bunches must be injected into and extracted from DR bunch-by-bunch. Then, the width of kicker pulse must be less than double of DR bunch spacing. According to the baseline design of ILC, the circumference of DR is 6.7k m, and bunch spacing is about 6ns/3ns. What kind of fast kicker is required? 4 ILC DR kicker system Parameters of the ILC DR kicker

The main features of DR kicker: Very short pulse (<12ns/6ns) High repetition rate in burst mode (=3M/6MHz) A strip-line kicker system with fast pulser wa s proposed. There are 21 kickers for injection an d 11 for extraction, so a long straight section is n eeded. 10ns/4ns 300ns/150ns 1ms 200ms 5 Strip-line kicker for ILC DR There are 2 strip-line kickers for ILC under beam test: ANE , LNF-INFNTF , KEK DANE , LNF-INFNNE , LNF-INFNNE , LNF-INFN 6 What is strip-line kicker?

Strip-line kicker is different with the conventional kicker magnet. The ch arged particle is deflected by travelling electro-magnetic wave, not by stand magnetic field. So, it can be called TW kicker. There are 2 parallel strip transmission lines in vacuum chamber, which used to transmit pulse EM wave in TEM mode. If a charged particle travels a direction opposite to that of the TEM wave with v=c, the particle experiences a transverse kick due to both electric field and magnetic field with FE=FB. Uq FE B 2 d eU l W d e2 x 1 tanh( x) 2 x e 1 E B 2 E 2 g g tanh( w ) 2d +

beam - TEM B E 7 How fast is strip-line kicker? In order to kick individual bunches by maximum deflection without affecting the adjacent bunches, the electrical pulse width (tp ) and length(l) of strip-line kicker must meet: U t t tp deflection tf

2l/c 2l/c 2l / c t p 2 2 l / c , l c / 2 There is bunch spacing, g=2l/c is call kick growth time. So, for ILC DR, =3ns/6ns ns/6ns : l =3ns/6ns 00mm<450mm, 2ns

8 following bunch Potential fast pulse technologies Commercial MOSFET (DEI-IXYS ) RF MOSFET Solid-state switches Power Transmission line adder (SLAC) Die form MOSFET MOSFET module (BEHLKE Gmbh) Inductive adder (LLNL,IHEP) Repetition Rate

Shift phase adder (DESY) Drift Step Recovery Diode(DSRD) +FID (FID Gmbh) Special Diode ` Drift Step Recovery Diode (DSRD)+MOSFET (Russia, Non commercial) (SLAC+DTI+Ioffe Institute) opening Others ` closing CSD DSRD IRD S OS SANE , LNF-INFNS (DBD) FID RSD 9 Three typical fast pulser for ILC kickers BEHLKE MOSFET SWITCH MODULE FID GmbH. FPG 5-3000M DESY HTS-50-08-UF

LLNL switch FID/DSRD MOSFET module (BEHLKE) RF power MOSFET (DEI_IXYS) 10 Fast pulsed power supply R&D for ILC DR kicker in IHEP The activity of R&D on fast pulsed source began in IHEP from 2009 sup ported by National Natural Foundation of China. The goal of our research is to build a performance evaluation prototype with: Width of pulse <10ns, Amplitude of pulse >5kV into 50 ,

Burst repetition rate >1MHz. Our research mainly focuses on the principle and the method of fast pul se technologies, such as: Pulse power stacking topology, RF MOSFET driver circuit, By commercial electronics as possibly, no patent components. Here, weve some experiences on fast pulsed source R&D to be shared: 11 The characteristics of ultra-short pulse Fourier transform graph of pulse of : 2ns 2ns Easy to know, an ultra-sho rt pulse has extended into mi crowave range. Generally, th e analysis method: 2ns circuitand lumped parameter If size>/20/20

0.2GHz 1GHz 2GHz waveand distributed parameter (There, is wavelength of the highest order harmonic ) 12 1. Fast pulse stacking topology There are 3 popular topologies for fast pulse stacking: Series switch (The BHELKE switch module maybe?) Inductive adder (Its mature tech. researched in LLNL for more than 15 years.) Transmission line transformer adder (Its an old concept in microwave tech., but still need to R&D for real application. ) On the first step, we selected inductive adder solution to start our research. Series switch topology

Inductive adder topology Transmission line adder topology 13 Topology study by PSPICE 0.5KV 0.0KV -0.5KV -1.0KV -1.5KV -2.0KV -2.5KV 1.0351us V(SA) V(SB) 1.0400us V(SC) V(SD)

1.0450us V(SE) V(SF) 1.0500us V(SH) V(SI) 1.0550us V(SJ) 1.0600us 1.0650us 1.0700us 1.0750us 10-stage inductive adder schematics in PSPICE V(SG) Time 14 1.0800us

2. Coaxial transformer design The coaxial transformer design is a key to inductive adder. A coaxial struct ure is an efficient method to reduce the leakage inductance of transformer. Bes ides it, the magnetic material of core is also critical for the fast pulse transform er. The nano-crystal core annealed in transverse magnetic field was selected. The stacking transformer is a kind of fraction ratio transformer : Tp:Ts=(1/N):1=1:N. 15 Considerations from the view of circuit As a lumped component , the length of coaxial transformer cell must meet: l / 20 15m m ( B W 1G H z ) A stacking transformer is equivalent to a LC low-pass filter net, so: fc 1 1 c

6 .4 G H z 1G H z l LC l L0C 0 C12 LS1 2C12 2C12 LM 2C12 LS2 LS2 LS2 LS2 2C12 2C12 LS2

C12 ( l 1 5 m m ) 2C12 C12 LS2 C12 C12 16 Considerations from the view of wave Every cell of the coaxial transformer can be regarded as a pulse source, whi ch drives into the load by a length of coaxial transmission line. So, the transmissi on line effect of the coaxial transformer must be considered: At the load end, the superposed pulse must be slowed down because of the deferenc e of transmission delay . if 1ns L 300 mm , N 20 (l 15mm ) -0V first stage

-100V Last stage 612p -200V -300V 1.050us V(SA) 1.051us V(SB) V(SC) 1.052us V(SE) V(SF) 1.053us V(SG) V(SH) 1.054us V(SI) V(SJ) 1.055us 1.056us

1.057us 1.058us 1.059us 1.060us every stage pulse transmit to load end V(SD) Time The coaxial structure must meet TEM mode transmission condition: r r ( D d ) / 2 Impedance of coaxial structure must match to the load: Z Z0 2 r ln (

D ) d , Z 0 377 17 Physical design of coaxial transformer It is optimal physical design for a single cell of coaxial transformer with taking all considerations mentioned above: 10mm 12mm 23mm 58mm There are 3 coaxial structures : R1&R2, R1&R3, R4&R5. R4 R5 conductor dielectric

R3 B B R2 B R1 B R1 core conductor Cross section of coaxial transformer 18 Structural design of coaxial transformer The structure design by SolidWorks: Cross-section of a single cell Cross-section of 10-stage module

Assembled inductive adder 19 3. RF switch circuit design RF switch circuit technology is the other key to all kind of a dders. Usually, The switch circuit includes: MOSFET array (easy to parallel because RON is positive temperature coefficient) Storage capacitor bank (work in DC mode) Drive circuit Transient voltage protection circuit 20

Power MOSFET At present, Power MOSFET is the fastest switching device in commer cial electronics. Its switching speed limit is imposed by two factors: transit time of electrons across the drift region (It is about 20-200ps depending on size of the device. ) the time required to charge and discharge the input Gate and Miller ca pacitances (It is limit by die package and drive circuit.) Power MOSFET: Double-diffused MOS CGD=CRSS CGS=CISS-CRSS CDS=COSS-CRSS Complete MOSFET model 21 DE-series RF Power MOSFET DE-series MOSFET(IXYS-DEI) is special designed for RF application, wit h specially die package, die topology and thermal dissipation structure. The selected MOSFET is: DE275-102N06A BVDSS ID PDC

Td(on ) TON Td(off ) TOFF 1000V 48A 590W CISS COSS CRSS 1800pF 130pF 25pF 3ns RDS 1.6 2ns

LG 1nH 4ns LD 1nH 5ns LS 0.5nH 22 Power MOSFET driver circuit As a switch, MOSFET must be driven from a low impedance source capa ble of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. There are 2 classes driver: Integrated driver (drive ability is limited, Io<20A) Driver type Vo Io Drive ability

(capacitor load/charge voltage Delay time(TONDLY/TOFFDLY) Min. pulse length Output impedance Power Level of input trigger DE275 switch speed 1kV into 50 TON/TOFF EL7158 12V 12A 12ns 2nf/ 12v 22ns/22.5ns 8ns 0.5 TTL(>3.5V ) -/- IXDN414 4.5-35v 14A

IXDD415 8-30V 15A DEIC420 8-30V 20A 22ns (15nf/18v) 4.5ns (4nf/15v) 4ns (4nf/15v) 30ns/31ns 10-15ns 0.6 12.5W 32ns/29ns 6ns 0.8 12W

32ns/29ns 8ns 0.4 100W TTL(>3.5V) TTL(>3.5V) TTL(>3.5V) 10ns/15ns 10ns/15ns 6ns/14ns Discrete component driver (usually a totem-pole topology) 23 Bipolar totem-pole Driver In this driver, the power MOSFET is turned on and off by two sequential clocks i ndependently via bipolar driving totem-pole. It is a current source driver instead of th e traditional voltage source driver. The key difference is that: drive voltage: V > Max. of V

SS GS of Q1 , drive current: I = V /(R of Q + R of M ). SS g 1 on 1 24 MOSFET switch circuit PCB layout sink DE275 storage capacitor transformer 25 MOSFET protective circuit There are 2 popular protective circuits:

storage capacitor primary protective circuit (A) storage capacitor primary secondary protective circuit secondary (B) The circuit (B) is selected for convenience of assembling. The circuit

is designed as an independent PCB, which is directly connected to the primary of coaxial transformer for lower stray inductance. Switching circuit board Protective circuit board 26 Final PCB designs of prototype Switching board and protector board 27 The prototype assembling 2-staget inductive adder 10-stage inductive adder 28 1-stage inductive adder test result Conditions U=250V PRF=1MHz RL=7.7 10X attenuation Result Front edge of pulse(10%-90% =1.9ns Width of pulse(FWHM) 10ns

PRF=1MHz 29 10-stage inductive adder test result Conditions U=610V PRF=1kHz RL=50 30dB attenuation Result Front edge of pulse(10%-90% =2.58ns Width of pulse(FWHM) 10ns Pulse amplitude 4kV 30 References ILC Global Design Effort and World Wide Study, International Linear Collider R eference Design Report, 2007 T. Naito, KEK, Development of Strip-line Kicker System for ILC Damping Ring,

Proceedings of PAC07, Albuquerque, New Mexico, USA, 2007 David Alesini, LNF-INFN, Fast RF Kicker Design, ICFA Mini-Workshop on Defl ecting/Crabbing Cavity Applications in Accelerators, Shanghai, April 23-25, 20 08 T. Naito, KEK, Fast kicker study, TB meeting, 2011/01/14 Craig Burkhart, SLAC. Ed Cook, C. Brooksby LLNL. Inductive Adder Modulato rs for ILC DR Kickers, ILC DR workshop, September 26, 2006 T. Tang, and C. Burkhart, SLACK, Hybrid MOSFET/Driver for Ultra-Fast Switc hing 31 Thank you for attention!