Linearly Compressed Pages: - Carnegie Mellon University
Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency Gennady Pekhimenko Advisers: Todd C. Mowry & Onur Mutlu Executive Summary Main memory is a limited shared resource Observation: Significant data redundancy Idea: Compress data in main memory Problem: How to avoid latency increase? Solution: Linearly Compressed Pages (LCP): fixed-size cache line granularity compression 1. Increases capacity (69% on average) 2. Decreases bandwidth consumption (46%) 3. Improves overall performance (9.5%) 2
Challenges in Main Memory Compression 1. Address Computation 2. Mapping and Fragmentation 3. Physically Tagged Caches 3 Address Computation Cache Line (64B) Uncompressed Page Address Offset 0 Compressed Page Address Offset L1 L0 0
TLB L2 Cache Lines tag tag tag Address Translation Physical Address data data data 6 Shortcomings of Prior Work Compression Access Decompression Complexity Compression Mechanisms Latency Latency Ratio IBM MXT [IBM J.R.D. 01]
7 Shortcomings of Prior Work Compression Access Decompression Complexity Compression Mechanisms Latency Latency Ratio IBM MXT [IBM J.R.D. 01] Robust Main Memory Compression [ISCA05]
8 Shortcomings of Prior Work Compression Access Decompression Complexity Compression Mechanisms Latency Latency Ratio IBM MXT [IBM J.R.D. 01] Robust Main Memory Compression [ISCA05]
LCP: Our Proposal
9 Linearly Compressed Pages (LCP): Key Idea Uncompressed Page (4kB: 64*64B) 64B 64B 64B 64B ... 64B 4:1 Compression ... Compressed Data (1kB) M
E Exception Storage Metadata (64B): ? (compressible) 10 LCP Overview Page Table entry extension compression type and size extended physical base address Operating System management support 4 memory pools (512B, 1kB, 2kB, 4kB) Changes to cache tagging logic physical page base address + cache line index (within a page) Handling page overflows Compression algorithms: BDI [PACT12] , FPC [ISCA04]
11 LCP Optimizations Metadata cache Avoids additional requests to metadata Memory bandwidth reduction: 64B 64B 64B 64B 1 transfer instead of 4 Zero pages and zero cache lines Handled separately in TLB (1-bit) and in metadata (1-bit per cache line) Integration with cache compression BDI and FPC 12
Methodology Simulator x86 event-driven simulators Simics-based [Magnusson+, Computer02] for CPU Multi2Sim [Ubal+, PACT12] for GPU Workloads SPEC2006 benchmarks, TPC, Apache web server, GPGPU applications System Parameters L1/L2/L3 cache latencies from CACTI [Thoziyoor+, ISCA08] 512kB - 16MB L2, simple memory model 13 C o m p r e s s io n R a ti o Compression Ratio Comparison SPEC2006, databases, web workloads, 2MB L2 cache 3.5 3 Zero Page
1 GeoMean LCP-based frameworks achieve competitive average compression ratios with prior work 14 N o r m a liz e d B P K I Bandwidth Consumption Decrease Better SPEC2006, databases, web workloads, 2MB L2 cache 1.2 1 0.8 0.6 0.4 0.2 0
23.6% 4 10.7% 22.6% 22.5% LCP frameworks significantly improve performance 16 Conclusion A new main memory compression framework called LCP(Linearly Compressed Pages) Key idea: fixed size for compressed cache lines within a page and fixed compression algorithm per page LCP evaluation:
Increases capacity (69% on average) Decreases bandwidth consumption (46%) Improves overall performance (9.5%) Decreases energy of the off-chip bus (37%) 17 Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency Gennady Pekhimenko Advisers: Todd C. Mowry & Onur Mutlu
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