Introduction - Mr.Rajiv Bhandari

Microprocessor and interfacing techniques 1 Prerequisites: Microprocessor Architecture Course Objectives: 1. To learn the Peripheral architecture and programming 0f Microprocessor. 2. To learn peripherals and their interfacing with 8086 Microprocessor. 3. To study the DOS Internals. 4. To Study NDP and Design of

Microprocessor based System. Course Outcomes: 1.Ability to handle, interface and program using legacy peripherals 2.Ability to understand I/O Hub functions 2 Books 80386 Tata Mcgraw Hill Turley Adv microprocessors and peripherals - Tata Mcgraw Hill Ray Microprocessors and interfacing McGraw Douglas Hall

Advanced MS DOS programming Ray Duncan Assembly language programming Pearson Peter Abel 3 Bits and bytes 1 Bit = Binary Digit 8 Bits = 1 Byte 1024 Bytes = 1 Kilobyte 1024 Kilobytes = 1 Megabyte 1024 Megabytes = 1 Gigabyte

1024 Gigabytes = 1 Terabyte 1024 Terabytes = 1 Petabyte 1024 Petabytes = 1 Exabyte 1024 Exabytes = 1 Zettabyte 1024 Zettabytes = 1 Yottabyte 1024 Yottabytes = 1 Brontobyte 1024 Brontobytes = 1 Geopbyte 4 What is a microprocessor? An integrated circuit that performs the functions of a CPU. So, a chip on machine

Which microprocessors do you know? 8085,8086,80285,80386,486,pentium.. Which is latest? Intel core i3, i5, i7 What type of processor? 16 or 32 or 64? 5 32 or 64 bit? What determines that my machine is 32 or

64? Amount of data that can be handled The RAM support for 32 bit is 4 GB where as for 64 it is 16EB. 64 bit of course leads to faster operations. 6 What is 8086? It is a 16 bit p. 8086 has a 20 bit address bus can access up to 220 memory locations ( 1 MB) . It can support upto 64K I/O ports.

It provides 14, 16-bit registers. It has multiplexed address and data bus AD0AD15 and A16 A19. 7 Architecture - 8086 8 Architecture of 8086 8086 has two blocks BIU and EU. The BIU performs all bus operations such as

instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. 9 Architecture of 8086 ctd BIU and EU operate asynchronously to give the 8086 an overlapping instruction fetch and

execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuit, Instruction decoder, ALU, 10 Pointer and Index register, Flag register Architecture of 8086 ctd

Bus Interface Unit: It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a 11

pipeline architecture. Architecture of 8086 ctd EXECUTION UNIT : The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.

During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the 12 instruction. Pin diagram - 8086 13 Important Pin descriptions AD0-Ad15: Multiplexed memory/IO address and data bus.

ALE: High the lower order bits to be latched, then these can be used for the data. READY: Acknowledgement from addressed memory or IO that it will complete the operation. INTR: Level triggered input, helps in determining whether the processors should enter into interrupt ack operation. A subroutine is vectored through an interrupt vector table. INTA: interrupt ack from the Microprocessor RESET: Causes processor to terminate its present activity. Signal must be high fro atleast 4 14 clock cycles. Restarts the execution.

Pin descriptions AD0-Ad15: Multiplexed memory/IO address and data bus. ALE: High the lower order bits to be latched, then these can be used for the data. READY: Acknowledgement from addressed memory or IO that it will complete the operation. INTR: Level triggered input, helps in determining whether the processors should enter into interrupt ack operation. A subroutine is vectored through an interrupt vector table. INTA: interrupt ack from the Microprocessor

RESET: Causes processor to terminate its present activity. Signal must be high fro atleast 4 15 clock cycles. Restarts the execution. Common signals for 8086 16 The Programming Model 8086 General Purpose Registers Segment Registers

Flag Register Pointer and index Registers SP AX AH AL CS BX


DL SS CX DX General Purpose Segment Registers BP

SI DI Flag Flag Register IP Pointer and Index Registers 17 Registers Organisation

16-Bit General Purpose Registers can access all 16-bits at once can access just high (H) byte, or low (L) byte only the General Purpose registers allow access as 8-bit High/Low sub-registers 18 Registers Organisation (continued)

Register Set 16-Bit Segment Addressing Registers CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment 19 Registers Organisation (continued) 16-Bit Offset Addressing Registers SP Stack Pointer BP Base Pointer

SI Source Index DI Destination Index 20 Registers Organisation (continued) 16-Bit Control/Status Registers - IP Instruction Pointer (Program Counter for execution control) - FLAGS 16-bit register It is not a 16-bit value but it is a collection of 9 bit-flags (six are unused) Flag is set when it is equal to 1

Flag is clear when it is equal to 0 21 General purpose Registers AX Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations

Must also be used in I/O operations 22 General purpose Registers (conti..) BX Base Register Also serves as an address register Used in array operations 23 General purpose Registers (conti..)

CX Count register Used as a loop counter Used in shift and rotate operations DX Data register Used in multiplication and division Also used in I/O operations 24 Pointer & Index Registers

Contain the offset addresses of memory locations Can also be used in arithmetic and other operations SP: Stack pointer Used with SS to access the stack segment 25 Pointer & Index Registers (continued) BP: Base Pointer Primarily used to access data on the stack Can be used to access data in other segments

SI: Source Index register is required for some string operations When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations. 26 Pointer & Index Registers (continued) DI: Destination Index register

is also required for some string operations. When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations. The SI and the DI registers may also be used to access data stored in arrays 27 Segment Registers

Are Address registers Store the memory addresses of instructions and data Memory Organization Each byte in memory has a 20 bit address starting with 0 to 220-1 of addressable memory 28 Segment Registers (continued) Addresses are expressed as 5 hex digits from 00000 - FFFFF Problem: But 20 bit addresses are TOO BIG to

fit in 16 bit registers! Solution: Memory Segment Block of 64K (65,536) consecutive memory bytes A segment number is a 16 bit number 29 Segment Registers (continued) Segment numbers range from 0000 to FFFF Within a segment, a particular memory location is specified with an offset An offset also ranges from 0000 to FFFF

30 Segment Registers (continued) If the segment address is for example, 2915, then the addresses in this segment start at 2915:0000 and go up to 2915:FFFF, which is the highest address in this particular segment. This range expressed in terms of absolute or physical addresses is from 29150 through 3914F. The relationship between a segment and the register which defines it is shown below.

31 Segment Registers (continued) Memory Model for 20-bit Address Space 32 Memory Segmentation 33 Memory Segmentation

34 Memory Address Generation Offset Value (16 bits) Segment Register (16 bits) 0000 Adder Physical Address (20 Bits)

35 Memory Address Generation to calculate physical memory address 36 Flag Register Carry flag Overflow

Parity flag Direction Interrupt enable Auxiliary flag Trap 6 are status flags 3 are control flag 37

Zero Sign Pinout Diagram 38 Minimum mode operation Ground Power Supply 5V 10%

Reset Registers, seg regs, flags Clock Duty cycle: 33% 39 CS: FFFFH, IP: 0000H If high for minimum 4

clks Minimum mode operation ( Conti..) Address/Data Bus: Contains address bits A15-A0 when ALE is 1 & data bits D15 D0 when ALE is 0. 40

Address Latch Enable: When high, multiplexed address/data bus contains address information. Minimum mode operation ( Conti..) INTERRUPT Non-maskable

interrupt Interrupt request 41 Interrupt acknowledge Minimum mode operation ( Conti..) Memory Access Hold

Hold acknowledge 42 Minimum mode operation ( Conti..) S6: Logic 0. S5: Indicates condition of IF flag bits. S4-S3: Indicate which segment is accessed during

current bus cycle: 43 Address/Status Bus Address bits A19 A16 & Status bits S6 S3 Minimum mode operation ( Conti..) BHE#, A0: 0, 0: Whole word

(16-bits) 0,1: High byte to/from odd address 1,0: Low byte to/from even address 1,1: No selection 44 Bus High Enable/S7 Enables most

significant data bits D15 D8 during read or write operation. S7: Always 1. Minimum mode operation ( Conti..) Min/Max mode Minimum Mode: +5V Maximum Mode: 0V Min mode pins

45 Minimum mode operation ( Conti..) When 1, transmit mode, when 0 receive mode from memory or IO Indicates the availability of valid data over address and data lines. Active from t2 to t4

46 Determined by wait instruction, when goes low, continue else idle Minimum mode operation ( Conti..) Read Signal Write Signal Memory or I/0

Data Bus Enable 47 Maximum mode operation 48 Maximum mode operation ( Conti..) 49 Maximum mode operation ( Conti..)

S2 S1 S0 000: 001: 010: 011: 100: 101: 110: 111: 50 INTA

read I/O port write I/O port halt code access read memory write memory none -passive Status Signal Inputs to 8288 to generate eliminated signals due to max mode.

Maximum mode operation ( Conti..) DMA Request/Gra nt 51 Maximum mode operation ( Conti..) Lock Output Used

to lock peripherals off the system Activated by using the LOCK: prefix on any instruction 52 Lock Output

Maximum mode operation ( Conti..) QS1 QS0 00: Queue is idle 01: First byte of opcode Queue Status 10: Queue is empty Used by numeric coprocessor (8087)

11: Subsequent byte of opcode 53 8288 Bus Controller Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces. Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it

outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow. S2S1S0 are input to the external bus controller device, the bus controller generates the appropriately timed command 54 Min-Max modes Min mode 1. MN/MX

Max mode high MN/MX low 2. Generates INTA(bar), ALE, DEN(bar), DT/R(bar), M/IO(bar), HLDA,HOLD and WR(bar) control signals.

Generates QS1, QS0, S0(bar) ,S1(bar) , S2(bar),LOCK(bar),RQ(bar)/GT1, RQ(bar)/GT0 control signals. 3. There is only one processor in the system clearly there are multiple processors in the system 4. No interfacing or master/slave

signals is required interfacing, master/slave and multiplexing and several such control signals are required 5. Direct RD WR signals can be used. No bus controller required. A simple demultiplexer would do the job. of producing the control signals. This demultiplexer produces MEMRD, MEMWR, IORD, IOWR control signals

A bus controller is required to produce control signals. This bus controller produces MEMRDC, MEMWRC, IORDC, IOWRC, ALE, DEN, DT/R control signals 55 Segmentation in 8086 16 bit MP. Can access 1MB of memory. Memory divided into 16 segments.

Each segment is 64KB. 56 80386 57 What is 80386?

A 32 bit micro processor Chip has 132 pins Total of 129 instructions 32 bit data bus and 32 bit address bus Executions in highly pipelined S/w written for 8086, 80186,80286 will run on 386. Available in 2 versions; DX and SX. DX: 32 bit data and address bus. 132 pins whereas for SX: 24 bit address and

16 bit data bus available. What is 80386? Makes use of 80387 co-processor. Can operate in 2 modes: Real Protected (virtual is within protected mode) Architecture Architecture of 80386 The Internal Architecture of 80386 is divided into 3 sections.

Central processing unit Memory management unit Bus interface unit Central processing unit is further divided into Execution unit and Instruction unit. Execution unit has 8 General purpose and 8 Special purpose registers which are either used for handling data or calculating offset addresses. Architecture The Instruction unit decodes the opcode bytes received from the 16-byte instruction code queue

and arranges them in a 3- instruction decoded instruction queue. After decoding them pass it to the control section for deriving the necessary control signals. The barrel shifter increases the speed of all shift and rotate operations. The multiply / divide logic implements the bitshift-rotate algorithms to complete the operations in minimum time. Even 32- bit multiplications can be executed within one microsecond by the multiply / divide logic. Architecture ctd

The Memory management unit consists of a Segmentation unit and a Paging unit. Segmentation unit allows the use of two address components, viz. segment and offset for relocability and sharing of code and data. Segmentation unit allows segments of size 4Gbytes at max. The Paging unit organizes the physical memory in terms of pages of 4kbytes size each. Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages.

Architecture ctd The Segmentation unit provides a 4 level protection mechanism for protecting and isolating the system code and data from those of the application program. Paging unit converts linear addresses into physical addresses. Each of the pages maintains the paging information of the task. Architecture ctd.. The Bus control unit has a prioritizer to resolve the priority of the various bus

requests. This controls the access of the bus. The address driver drives the bus enable and address signal A0 A31. The pipeline and dynamic bus sizing unit handle the related control signals. The data buffers interface the internal data bus with the system bus. Pin diagram of 80386 Signal descriptions of 80386

67 CLK2 :The input pin provides the basic system clock timing for the operation of 80386. D0 D31:These 32 lines act as bidirectional data bus during different access cycles. A31 A2: These are upper 30 bit of the 32- bit address bus. BE0 to BE3: The 32- bit data bus supported by 80386 and the memory system of 80386 can be viewed as a 4- byte wide memory access mechanism. The 4 byte enable lines BE0 to BE3, may be used for enabling these 4 banks. Using these 4 enable signal lines, the

CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously. W/R#: The write / read output distinguishes the write and read cycles from one another. D/C#: This data / control output pin distinguishes between a data transfer cycle from a machine control cycle like interrupt acknowledge. M/IO#: This output pin differentiates between the memory and I/O cycles.

LOCK#: The LOCK# output pin enables the CPU to prevent the other bus masters from gaining the control of the system bus. NA#: The next address input pin, if activated, allows address pipelining, during 80386 bus cycles. 69 Descriptions ctd ADS#: The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The 80386 does not have any ALE signals and so this signals may be used for

latching the address to external latches. READY#: The ready signals indicates to the CPU that the previous bus cycle has been terminated and the bus is ready for the next cycle. The signal is used to insert WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU. VCC: These are system power supply lines. VSS: These return lines for the power supply. 70 Descriptions ctd BS16#: The bus size 16 input pin allows the

interfacing of 16 bit devices with the 32 bit wide 80386 data bus. Successive 16 bit bus cycles may be executed to read a 32 bit data from a peripheral. HOLD: The bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted. HLDA: The bus hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU. BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy with the

71 allocated task. Descriptions ctd ERROR#: The error input pin indicates to the CPU that the coprocessor has encountered an error while executing its instruction. PEREQ: The processor extension request output signal indicates to the CPU to fetch a data word for the coprocessor. INTR: This interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register. NMI: A valid request signal at the non-maskable

interrupt request input pin internally generates a nonmaskable interrupt. RESET: high at this input pin suspends the current operation and restart the execution from the starting location. N / C : No connection pins are expected to be left open while connecting the 80386 in the circuit. 72 Registers in 80386 The 80386 has eight 32 - bit general purpose registers which may be used as either 8 bit or 16 bit registers. A 32 - bit register known as an extended register,

is represented by the register name with prefix E. Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc. The 16 bit registers BP, SP, SI and DI in 8086 are now available with their extended size of 32 bit and are names as EBP,ESP,ESI and EDI. AX represents the lower 16 bit of the 32 bit register EAX. BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent 16 bit registers. 73

Registers of 80386 74 More about registers and flag register The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS. The CS and SS are the code and the stack segment registers respectively, while DS, ES, FS, GS are 4 data segment registers. A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP.

Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extra new flags are added to the 80286 flag to derive the flag register of 80386. They are VM and RF flags. 75 Flag register 80386 76 More about flag bits:

VM - Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode within the protection mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception 13 is generated. This bit can be set using IRET instruction or any task switch operation only in the protected mode. RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions.

Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instruction causing a task switch. These instruction are used to set the RF to the value specified by the memory data available at the stack. 77 Segment Descriptor Registers The registers are not available for programmers, rather they are internally used to store the descriptor information, like attributes, limit and base addresses of segments.

The six segment registers have corresponding six 73 bit descriptor registers. Each of them contains 32 bit base address, 32 bit base limit and 9 bit attributes. These are automatically loaded when the corresponding segments are loaded with selectors. 78 Control and system address registers Control Registers: The 80386 has three 32 bit control registers to hold global machine status independent of the executed task. Load and store

instructions are available to access these registers. System Address Registers: Four special registers are defined to refer to the descriptor tables supported by 80386. The 80386 supports four types of descriptor table, viz. global descriptor table (GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task state segment descriptor (TSS). 79 Debug and test registers

Intel has provide a set of 8 debug registers for hardware debugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are Intel reserved. The initial four registers DR0 to DR3 store four program controllable breakpoint addresses, while DR6 and DR7 respectively hold breakpoint status and breakpoint control information. Two more test register are provided by 80386 for page caching namely test control and test status register.

80 Address calculations in 80386 real mode 81 Protected mode: segment translation Logical(Virtual) Address Segmentation

Unit Linear Address Base Address in LDTR Register Base Address in GDTR Register Segment descriptor

Linear Address Paging Unit Physical Address Paging is enabled Logical to Physical address translation in 80386 The 80386 has three address spaces: logical, linear, physical

The 80386 transforms logical addresses (i.e., addresses as viewed by programmers) into physical address (i.e., actual addresses in physical memory) in two steps: Segment translation, in which a logical address (consisting of a segment selector and segment offset) are converted to a linear address. Page translation, in which a linear address is converted to a physical address. This step is optional, at the discretion of systems-software 88 Logical to Physical address

translation in 80386 Logical address contains selector and offset Selector used to point descriptor in the descriptor table by using index field in it. 32 bit linear address is calculated by adding base address of descriptor and 32 bit offset. If paging is not enabled then linear address=physical address If paging is enabled then linear address is converted into physical address. It is called as paging translation. 89

Timing diagram of 8086 Timing diagrams - terminologies Shows the graphical representation of the timing and control signal generated when instruction is been executed. Instruction cycle: Fetch + execute One cycle of the clock is called state. A state is measured from falling edge. Time interval t1 is a state. T- states: portion of an operation performed in one clock period

If for example - Frequency is 2MHz the oscillator generates 2^6 t states per second. 8086 frequencies vary from 5 MHz to 10 MHz. so minimum time for 1 t state is between 100 and 200 ns. 91 Types of operations 1. 2. 3.

4. 5. Opcode fetch Memory read Memory write I/O read I/O write 92 Read timing diagram

93 Address decoding Memory mapped IO IO mapped IO Memory mapped IO Uses the same address bus to address both memory and I/O devices, and the CPU instructions used to access the memory are also used for accessing devices IO mapped IO Uses a special class of CPU instructions specifically for performing I/O. Specifically the IN and OUT

instructions which can read and write one to four bytes to an I/O device. I/O devices have a separate address space from general memory 94

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