Integrated Circuits Group - Fermilab

Status of New Cold ADC Carl Grace (on behalf of Cold ADC Design Team) [email protected] July 16, 2018 Cold Electronics Workshop Advancing Science by Design Brookhaven National Laboratory ENGINEERING DIVISION Outline Introduction Block Details Design Review discussion of calibration algorithm simulations High-level validation and testing Conclusion Advancing Science by Design Carl Grace 2 ENGINEERING DIVISION Introduction Cold ADC is a 16-channel, 12-bit, 2 MS/s Digitizer ASIC to replace the current ADC ASIC Designed by joint team from LBNL, FNAL, and BNL Key design goal: first time success

Cold ADC uses a conservative, industry-standard design with digital self-calibration Besides functionality and reliability, design goal is lownoise operation Design contains significant features for risk mitigation and observability Advancing Science by Design Carl Grace 3 ENGINEERING DIVISION Chip Top-Level VDD/VSS domains Cold ADC IN0 BUFFER DIG_CLKOUT(P/N) S/H DIG_FRAME(P/N) DIG_OUTA(P/N) 16 30 8-1 MUX 12-bit 16 MS/s Pipelined ADC

16 DIG_OUTB(P/N) Calibration Engine Correction Logic DIG_OUTC(P/N) DIG_OUTD(P/N) DIG_OUTE(P/N) IN7 BUFFER DIG_OUTF(P/N) S/H DIG_OUTG(P/N) ADC Reference Buffers Data Formatter DIG_OUTH(P/N) LVDS I/O LVDS_REF IN8

BUFFER S/H CLK_64MHZ(P/N) 30 8-1 MUX 12-bit 16 MS/s Pipelined ADC 16 Correction Logic CLK_16MHZ(P/N) 16 CLK_2MHZ(P/N) Calibration Engine VMONITOR IN15 BNL BUFFER BUFFER + S2D LBNL

IMONITOR S/H BJT-based Reference Generation CMOS-based Reference Generation Configuration and Debug Interface I2C I2C_(SCL,SDA, SDO) UART MISO/MOSI FNAL I2C_ADD VREF(P,N,CMI,CMO), BGR SSO_(FRAME, DATA[1:0], CLK) Advancing Science by Design Carl Grace

4 ENGINEERING DIVISION Technology Choices ASIC implemented in 65 nm CMOS technology leverages existing FNAL cold models facilitates potential future integration with colDATA. Design follows conservative guidelines developed by BNL power supplies reduced by 10% minimum device length increased by 50% Analog blocks implemented with thick-oxide devices and high supply Relaxes noise requirements Simplifies interface with LArASIC ASIC implemented using a digital-on-top design style Advancing Science by Design Carl Grace 5 ENGINEERING DIVISION

Current Status Most Macro block layouts complete (LVS/DRC clean) All RTL synthesized. P&R being coordinated Padring and floorplan defined Top-level chip integration to commence this week Verification plan in-place and execution is on-going Cold ADC is on-track for summer submission Advancing Science by Design Carl Grace 6 ENGINEERING DIVISION Key Cold ADC Specs Specification Number of channels Sampling Rate Aggregate Output Data Rate Noise ADC Resolution ADC Linearity ENOB Input Range Value Units 16 (singleended or differential) 2 MS/s 512

Mb/s 175 V-rms 12 +/- 0.5 10.5 0 1.6 bits LSB bits V Note Channel rate 8 LVDS pairs at 64 Mb/s each < LArASIC noise w/ margin @ 12-bit level SNDR 65 dB Advancing Science by Design Carl Grace 7 ENGINEERING DIVISION Layout: 8-SHAs + ADC Reference buffers

15-stage Pipelined ADC 8 SHAs Block is about 3.2 mm by 3.2 mm Advancing Science by Design Carl Grace 8 ENGINEERING DIVISION Layout: Input Buffers + LBNL Ref 16 input buffers (single-to-diff and differential buffers) LBNL Reference Block (pitchmatched to SHA + ADC) Advancing Science by Design Carl Grace 9 ENGINEERING DIVISION Noise Partitioning What generates noise in the Cold ADC ASIC? Block Noise [V-rms] % total noise

ADC + SHA 155 76 Buffer 55 11 Reference 65 13 Total 177 100 Advancing Science by Design Carl Grace 10 ENGINEERING DIVISION Noise Partitioning Noise with ADC scaling and quantization

SHA STAGE 1 STAGE 2 OTHER STAGES INPUT BUFFER REFERENCES QUANTIZATION Referred to ASIC input (assuming 2X input buffer gain) Optimal power efficiency when thermal noise = quantization noise Advancing Science by Design Carl Grace 11 ENGINEERING DIVISION Design Methodology Design Phase Relative Cost of Error Requirements Specification 1 Behavioral Modeling 10 Schematic Design 100 Layout Design

500 Top-Level Integration 1000 After Tapeout Almost infinite Adapted from Boehm, Software Engineering, IEEE Trans. Comp. 12/76 Cold ADC is designed using a top-down methodology. All functional requirements, configuration settings, and interfaces were defined as accurately as possible before schematic design began Advancing Science by Design Carl Grace 12 ENGINEERING DIVISION Design Risk Mitigation BLOCK WORK-AROUND Buffer Bypass (directly connect LArASIC to ADC) ADC Reference Buffers Bypass (use external references)

Bandgap Reference Bypass (use CMOS-based reference, external BGR, or external references) Bias Currents Highly adjustable to improve settling or reduce power at cold (for instance) Calibration Algorithm Calibrate off-line and load gain estimates into register file Correction Logic Use uncalibrated (traditional) ADC output (expect about 10-bit linearity in this case) Digital Interface to colData Route ADC data through SSO (can still evaluate ADC performance) Configuration Interface Read and Write with either I2C or UART ADC Gain Boosting Include gain booster kill switch Advancing Science by Design

Carl Grace 13 ENGINEERING DIVISION Top-Level Design SystemVerilog model captures all specified functional requirements (e.g. configuration modes) Real-Number Modeling for Analog Circuits (including gain error, mismatch, etc), RTL modeling for Digital Circuits Use cloud-based tool (Smartsheet) to keep track of Functional Requirements, Configuration Bits, and Pad Definitions across sites Use tools (Cliosoft) for version control and tracking of design materials Advancing Science by Design Carl Grace 14 ENGINEERING DIVISION Verification Methodology RTL along with analog models is being verified using UVM, which is an industry standard verification methodology for digital designs. In addition, RTL is verified using regression functional testing, including code coverage, to ensure our tests exercise every line of code and every FSM state. Block interfaces and configurations are verified using VerilogAMS. This is a superset of Verilog with analog extensions which allow sophisticated, pinaccurate models of analog blocks to be cosimulated with RTL.

Advancing Science by Design Carl Grace 15 ENGINEERING DIVISION Input Buffer (BNL) 3 operating modes: 1. Fully differential 2. Converts from single-ended to differential 3. Bypassed (and powered down) used with potential differential-output LArASIC Noise of the buffer adds directly to the input, so must be significantly below total noise Converting to differential gives gain of 2 1.95 V

1.6 V SD VCMI 0.8 V VCMO 1.2 V 0V 0.45 V Advancing Science by Design Carl Grace 16 ENGINEERING DIVISION Input Buffer ibuff SDC sha_channel DB sdc_pd = 1 db_pd = 1 0V VIN inn out_sdc

outp<1> inp outn_sdc outn<1> von sha_se_input = 1 vop _ + vod VCMI sdc_pd = 1 db_pd = 1 rms noise = 55 V Closed-loop BW = 22 MHz Advancing Science by Design Carl Grace

17 ENGINEERING DIVISION Input Buffer Simulation Yellow is buffer output, red is sampled ADC signal. When put into tracking mode, buffer settles in less than 25 ns. Advancing Science by Design Carl Grace 18 ENGINEERING DIVISION Sample-and-Hold (SHA) The Sample-and-Hold amplifier (SHA) has 2 operating modes: 1. Fully differential 2. Converts from single-ended to differential (in case input buffer is bypassed) Samples at 2 MS/s but requires fast settling (< 30 ns) to prepare for ADC sampling Advancing Science by Design Carl Grace 19 ENGINEERING DIVISION SHA

vcmo CF 1 2 vcmi 1 CS vcmo 1 1p vip vop vop or vcmi 1 von 1p CS 1 vcmo vcmi These switches determine overall linearity CF 1 2

vcmo Switched-capacitor SHA uses standard design based on charge redistribution. Besides sampling, the SHA shifts common-mode voltage from input buffer to ADC Advancing Science by Design Carl Grace 20 ENGINEERING DIVISION SHA Clocking 2 MHz SHA sampling clock, 16 MHz ADC clock that can be adjusted in phase with respect to 2 MHz sampling clock. Sampling Clock ADC Clock 0 1 2 3 4 5 7 6

500 ns Advancing Science by Design Carl Grace 21 ENGINEERING DIVISION SHA Simulation (PEX) Continuous-time input Sampled-data output 70 SHA is only as linear as its input switch Input-switch Ron 30 0V Carl Grace 2.2 V Switch on-resistance < 65 across operating range Advancing Science by Design 22 ENGINEERING DIVISION

SHA Simulation (PEX) SHA output spectra 27 C SHA SNDR = 77.4 dB (~12.5 bits) -200 C SHA SNDR = 72.5 dB (~11.8 bits) Advancing Science by Design Carl Grace 23 ENGINEERING DIVISION ADC Top Level Pipelined ADC 1.5 bits 1.5 bits 1.5 bits 1.5 bits VR Vin Stage 1 V1 V in Stage

2 V2 Stage 3 V3 ... V14 2 SHA Stage 15 b=0 b=1 b=2 Vo VR/2 Vi 0 Vout -VR/2

Interstage amplifier 1.5 bits ADSC DASC -VR -VR/4 VR/4 ADC stage transfer characteristic Pipelined ADC capable of about 10-bits or so of raw accuracy (limited by cap mismatch and op amp finite gain) ADC block diagram Key point: gain errors dont inherently cause nonlinearity. It appears only when assumed gain (i.e. the stage radix) is wrong. Advancing Science by Design Carl Grace 24 ENGINEERING DIVISION VR Calibration Concept Vout/Vref Digital Out: 1

0 S0 2 S2 W2 = (S2-S3) Vin/Vref W0 = (S1-S0) S1 1+ () = 1 =1 2 S3 Size of jump = actual stage gain -1 -Vref/4 Vref/4 1 Need to measure this Ideally stage gain exact power of 2, it that case we can simply concatenate bits to generate output code Deviations from 2 nonlinearity Advancing Science by Design

Carl Grace 25 ENGINEERING DIVISION Calibration Concept (cont.) Use proven Karanicolas - Soenen algorithm converts unknown radix (depends on component matching and finite open-loop gain) to base-2 Technique based on fact that missing codes in ADC transfer characteristic can be corrected as long as all decision levels present Set input to decision level, force decision 1 & 0, drive difference to 0 Decision Weight Measurement 0 w0 S1-S0 1 0

N/A 2 w2 S2-S3 Vout/Vref Digital Out: 1 0 S0 2 S2 W2 = (S2-S3) Vin/Vref W0 = (S1-S0) S1 -1 -Vref/4 S3 Vref/4 1

1 = ( ) =0 Advancing Science by Design Carl Grace 26 ENGINEERING DIVISION Back-to-Front Calibration Stage under calibration Stages not yet calibrated Backend ADC Test signal Pseudocode: for STAGE (max downto 0) do Measure decision levels (S0, S1, S2, S3); Calculate stage weights (w0, w2); Write stage weights (w0, w2) to Register File; Next STAGE; end Advancing Science by Design Carl Grace

27 ENGINEERING DIVISION Calibration Hardware Config Interface Gain Estimate Updates Register File w0[0] w2[0] CELL 0 dec[0] w0[1] sum[0] w0[2] w2[1] CELL 1 dec[1] sum[1] w2[2] w0[n]

CELL 2 sum[2] sum[N-1] dec[2] Analog Input Calibration Engine w2[n] CELL N Corrected ADC Out To Serial Interface dec[n] Comparator Forcing Commands ADC CTRL w0 Calibrate up to seven stages in Cold ADC

CTRL 16 w2 Next Stage Previous Stage 1 = ( ) =0 16 Advancing Science by Design Carl Grace 28 ENGINEERING DIVISION Calibration Hardware (cont.) STG CNT ADC CTRL signals Correction Logic

OUT LAT CNT CYC CNT FINITE STATE MACHINE 16 16 32 16 w0,w2 estimates to Regfile 32 Digital calibration Engine. One for each ADC. Advancing Science by Design Carl Grace 29 ENGINEERING DIVISION Notes about ENOB ENOB is the number of bits of an ideal ADC that gives the same SNDR performance as the ADC being evaluated e.g. a 14-bit ADC with ENOB = 12.2 would have the same SNDR as

an ideal 12.2-bit ADC Ideal here means the only noise comes from the inherent uncertainty of quantization, and the ADC is perfectly linear (DNL = 0) =20 log 10 2 2 ( 2 (1+ ) + 12 3 ) (DNL and vn in units of LSB) Advancing Science by Design Carl Grace 30 ENGINEERING DIVISION Notes about ENOB (cont.) ENOB is related to the SNDR by: 1.76 =

6.02 Therefore, by specifying the noise and linearity, we are indirectly specifying what ENOB we really want. Advancing Science by Design Carl Grace 31 ENGINEERING DIVISION Notes about ENOB (cont.) For example, say we want a 12-bit ADC with 3 V swing, 0.5 LSB DNL, and 300 V-rms total input noise = 210 V, so vn = (3002 2102) = 214 V = 64.06 dB = 10.4 bits Thermal noise = quantization noise common in practice (lose 1b ENOB) 0.5 LSB DNL lose additional 1b ENOB Advancing Science by Design Carl Grace 32 ENGINEERING DIVISION Simulation Results (uncalibrated) ENOB spec = 10.5 bits Average ENOB = 9.4 bits

Yield = 6% Assume 15 stage converter. Op-amp gain = 2000, 0.5% cap matching, no calibration, rms thermal input noise 120 V, 100 trials Significant nonlinear distortion limits ENOB here Advancing Science by Design Carl Grace 33 ENGINEERING DIVISION Simulation Results (uncalibrated) DNL: -1.0/0.98 LSB INL: -3.8/4.1 LSB DNL & INL from typical instance of previous case Can see structure in linearity (no stages calibrated) Advancing Science by Design Carl Grace 34 ENGINEERING DIVISION Simulation Results (calibrated) ENOB spec = 10.5 bits Average ENOB = 11.1 bits Yield = 100%

Assume 15 stage converter. Op-amp gain = 2000, 0.5% cap matching, 8 calibrated stages, rms thermal input noise 120 V, 100 trials After calibration, ADC ENOB is noise limited. Advancing Science by Design Carl Grace 35 ENGINEERING DIVISION Simulation Results (calibrated) DNL: -0.18/0.15 LSB INL: -0.23/0.12 LSB DNL & INL from typical instance of previous case (8 stages calibrated) Note structure in linearity mostly removed Advancing Science by Design Carl Grace 36 ENGINEERING DIVISION Simulation Results (calibrated) Output spectrum from typical instance of previous case (8 stages calibrated) Advancing Science by Design

Carl Grace 37 ENGINEERING DIVISION ADC Simulation (schematic) 16-bit ideal DAC readback 13 kHz full-scale sine input Uncalibrated output Carl Grace Advancing Science by Design 38 ENGINEERING DIVISION ADC Stage Conceptual block diagram of ADC Stage 2 1 CF 1 CS Vin Vout

1p A VREF/4 2 VDASC Decoder B -VREF/4 MSB LSB + = VREF -VREF Capable of about 10-bits or so of raw accuracy (limited by cap mismatch and op amp finite gain) Advancing Science by Design Carl Grace 39

ENGINEERING DIVISION Stage MDAC 2 Cal Mux 1 Vcaln vDASCP Vcalp 1 2 CF vcm CS vcm 1 1p Vip vop 1p von Vcalp 1

Vcaln 2 1p CS 1 vcm vDASCN vcm CF Vin 1 2 Vcalp and Vcaln are decision levels generated internal to the stage Advancing Science by Design Carl Grace 40 ENGINEERING DIVISION MDAC Op amp VDDA

bias<6> Fully differential foldedcascode opamp w/ gain-boosting MPLOADN MPLOADP bias<5> Gain = 86 dB GBW = 177 MHz PM = 75 degrees Vip MNINP bias<2> MNINN Vin MPCASCP MPCASCN MNCASCP MNCASCN Von Vop

MNTAILC bias<3> bias<1> MNTAIL bias<1> MNLOADN CMC MNCM VSSA Advancing Science by Design Carl Grace 41 ENGINEERING DIVISION MDAC Op amp Gainboosters VDDA MPTAIL Vbias_tail MPINP Vip MPINN

Vin Vout MNOUT MNDIODE VSSA P-channel GB Gain = 39.5 dB GBW = 250 MHz PM = 69 degrees Advancing Science by Design Carl Grace 42 ENGINEERING DIVISION MDAC Op amp Gainboosters VDDA MPOUT MPDIODE Vout MNINP Vip

MNINN Vin Vbias_tail MNTAIL VSSA N-channel GB Gain = 45.5 dB GBW = 292 MHz PM = 65 degrees Advancing Science by Design Carl Grace 43 ENGINEERING DIVISION MDAC Op amp (PEX) GBW = 177 MHz Gain = 86 dB PM = 75 degrees Advancing Science by Design Carl Grace 44

ENGINEERING DIVISION Common-Mode Feedback 2 1 Vop 2 1 Vcm Vcm Ccmfb p Cflyp 2 2 1 Vcmc Cflyp 1 2 1 Vbias

Vbias 2 Cflyn 2 1 Ccmfb n Von 2 Cflyn 1 1 Vcm Vcm Conservative CMFB gives symmetric output loading reduced CM offset in exchange for larger CMFB load Advancing Science by Design Carl Grace 45 ENGINEERING DIVISION Stage MDAC (diff. settling PEX) differential output

common-mode output sampling clock Advancing Science by Design Carl Grace 46 ENGINEERING DIVISION Stage MDAC (cm settling PEX) differential output common-mode output sampling clock Common-mode settling after power-up is fast and accurate Advancing Science by Design Carl Grace 47 ENGINEERING DIVISION Stage ADSC A

VTHRESHP VTHRESHN 0 1 FORCE_MSB VIP MSB LSB LATCH VIN CALIB STAGE LOGIC X Y B VTHRESHN VTHRESHP Z 0 1 FORCE_LSB CALIB

LATCH A B MSB LSB X Y Z 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1

1 0 0 0 1 0 Stage Logic Truth Table VTHRESH{P/N} equal to Vcalp and Vcaln Advancing Science by Design Carl Grace 48 ENGINEERING DIVISION Switched-Capacitor Comparator 2 vcm VTHRESHP 1 CS 2 VIP OUT

S Regenerative Latch VIN 1 VTHRESHN 2 2 CS vcm LATCH R OUT Comparator samples signal and threshold in opposite clock phases Difference between them is latched and drives MDAC Offset is critical issue as errors larger than Vthresh/4 cannot be corrected by the calibration Advancing Science by Design Carl Grace 49 ENGINEERING DIVISION

Key Analog Requirement, Offset Offset Tolerance VR b=0 b=1 Assume +/- 1.5 V differential reference b=2 1st stage eff. bits Vo VR/2 Vi 0 Offset Tolerance Tolerance in mV 1 +/- VR/4 375 2 +/- VR/8

187.5 3 +/- VR/16 93.75 4 +/- VR/32 46.875 -VR/2 -VR -V R/4 V R/4 VR As much as 4X worse matching for offset may be expected at cold Stage overrange means lost analog information (in this case, decision levels) that cannot be recovered using calibration MUST AVOID Advancing Science by Design Carl Grace 50 ENGINEERING DIVISION

Comparator Core VDDA2P5 Latch Preamp MP3 VDDD2P5 LATCH MP5 MP2 MP6 LATCH MP8 MP4 Von Vop VDDD2P5 VDDD2P5 MN7 MP1 MN8

MP9 MP10 LATCH Vip MN1 Vbias_comp MN2 MN3 LATCH MN4 Vin LATCH MN5 MN6 VSSD VSSA Balanced latch minimizes dynamic mismatch current Advancing Science by Design Carl Grace

51 ENGINEERING DIVISION Comparator Simulation Room temperature Monte Carlo (400 runs) (ADC can tolerate 375 mV total offset) Advancing Science by Design Carl Grace 52 ENGINEERING DIVISION Key Analog Requirement, Offset Static offset is dominated by Vt mismatch Dynamic offset is suppressed by comparator preamp Vt mismatch: Expected offset (1):): Comparator core: 6.8 mV Comparator caps: 7.5 mV Comparator kT/C: 0.8 mV MDAC: 1.1 mV total = 10.2 mV (< 3% of correction range) f: Worse case: 4*(3):) = 122.4 mV About 3X design margin using 1.5 bits/stage Pipelined ADC Advancing Science by Design

Carl Grace 53 ENGINEERING DIVISION Reference Buffers Reference Buffers drive ADC reference voltages Reference voltages need to settle to better than about 0.25 LSB between samples (define settling time here as 1/3 clock period @ 20 MS/s for margin) Need Low Noise 1+ () = 1 =1 2 ideal Pipelined ADC transfer function. Digital output is the ratio of the input to the reference, not the input itself! Noise in reference directly couples to input of ADC Advancing Science by Design Carl Grace 54 ENGINEERING DIVISION Reference Buffers (cont.) Vrefp

10 Vrefp_internal Rthresh Vrefn 10 Vcmi 10 Vcmo 10 Vrefn_internal Vcmi_internal Vcmo_internal 10 resistors help settling for switched capacitor load Advancing Science by Design Carl Grace 55 ENGINEERING DIVISION Reference Buffers (cont.) To reduce power, use class AB Monticelli biasing VDDA

MP1 2*K1*IB IB VY MP2 VY MPCS MPCS VN VP MPB MNB VOUT Level-shift MN2 VX VIN VOUT IQ

VX MNCS IB MNCS MN1 2*K1*IB Iin VSSA D.M. Monticelli, A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing, IEEE Journal of Solid-State Circuits, vol. SC-21, pp. 1026-1034, Dec. 1986 Advancing Science by Design Carl Grace 56 ENGINEERING DIVISION Reference Buffers (cont.) 125 A 125 A 400 A 400 A 500 A

VDDA MP4 MP3 MP8 MP7 4 pF VB4 3.49 mW nominal VIP MP6 MP5 VB3 MP9 MP1 MP2 VIN VP VOUT VN

MP10 MN6 MN7 VB2 MN4 MN3 4 pF VB1 MN1 MN2 VSSA 525 A 525 A PMOS input version (for low-voltage references) Advancing Science by Design Carl Grace 57 ENGINEERING DIVISION Reference Buffers (cont.) 250 A 250 A 500 A VDDA

MP2 MP1 4 pF VB4 MP4 MP3 2.25 mW nominal VB3 MP5 VP MN1 VIN MP6 VOUT VN MN10 VIP MN2 MN9

VB2 MN7 MN8 4 pF VB1 MN3 MN4 MN5 MN6 VSSA 100 A 100 A 150 A 150 A NMOS input version (for high-voltage references) Advancing Science by Design Carl Grace 58 ENGINEERING DIVISION Reference Buffers (cont.) VDDA MPBIAS

MPVP1 MPTRI MPINA 4.5 mW nominal MPVN1 MPINC MPINB VB<4> MPVP2 MPC MPDIODE VB<3> IBIAS_IN MPVP3 VN MNVN3 MNC MNCASC1 MNCASC2

VP MNVP2 MNVN2 MNDIODE VB<2> VB<1> MNINA MNINB MNBIAS2 MNTRI MNBIAS3 MNVP1 MNVN1 MNBIAS1 VSSA 250 A 250 A 250 A 250 A 250 A

250 A 250 A 250 A Bias Circuit. High currents for low noise. Advancing Science by Design Carl Grace 59 ENGINEERING DIVISION Reference Buffers (PEX) DC Gain = 108 dB GBW = 61.6 MHz PM = 70.5 degrees Rout_ol = 50 k Rout_cl = 0.2 Unloaded AC analysis for PMOS-input ref buffer Advancing Science by Design Carl Grace 60 ENGINEERING DIVISION Reference Buffers (PEX) DC Gain = 134 dB GBW = 59.5 MHz

PM = 80 degrees Rout_ol = 70 k Rout_cl = 0.1 Unloaded AC analysis for NMOS-input ref buffer Advancing Science by Design Carl Grace 61 ENGINEERING DIVISION Reference Buffers (PEX) Output noise density RMS output noise = 125.5 V Differential noise of VREFP VREFN (including idealized resistive load) at room temperature (27 C) Cold specification is 50 V-rms. AC simulation does not include switched-capacitor filtering effects Advancing Science by Design Carl Grace 62 ENGINEERING DIVISION Reference Buffers (PEX) Output noise density RMS output noise =

64.5 V Differential noise of VREFP VREFN (including idealized resistive load) at LN2 temperature (-200 C) Cold specification is 50 V-rms. AC simulation does not include switched-capacitor filtering effects Advancing Science by Design Carl Grace 63 ENGINEERING DIVISION Reference Buffers (PEX) VREFP VREFN VREFD PHI1 PHI2 Reference settling VREFP VREFN at room temperature (27 C) including ADC load Advancing Science by Design Carl Grace 64 ENGINEERING DIVISION Reference Buffers (PEX) VREFP VREFN VREFD PHI1 PHI2 Reference settling VREFP VREFN at LN2 temperature

(-200 C) including ADC load Advancing Science by Design Carl Grace 65 ENGINEERING DIVISION Reference Buffers (PEX) VREFD PHI2P 100-run transient noise simulation (including ADC load). Peak-to-peak noise at sampling edge ~ 60 V-rms Advancing Science by Design Carl Grace 66 ENGINEERING DIVISION Reference Buffers (PEX) Scatter-plot of sampled reference values for 100-run transient noise simulation (including ADC load). Standard deviation ~ 15.9 V (well below specification)Advancing Science by Design Carl Grace 67 ENGINEERING DIVISION ADC Clocking

1p 1 CLK PD 2 2p Non-overlapping clocks for ADC produced from master clock Issue: will they overlap across temperature? Advancing Science by Design Carl Grace 68 ENGINEERING DIVISION ADC Clocking Clocking: fast corner, cold 400 ps is a conservative non-overlap time in 65 nm. Delay can be adjusted under digital control for additional insurance. Advancing Science by Design Carl Grace 69 ENGINEERING DIVISION Issue: ADC & digital clocks different t Calib Clock

ADC Phi1 ADC Phi2 Issue: difficult to constrain delay between calibration clock and ADC clocks. Delay is temperature dependent. Advancing Science by Design Carl Grace 70 ENGINEERING DIVISION Issue: ADC & digital clocks different The expected delay between CLK and PHI1 is 1.4 ns (cold) so probably not an issue. But what if there is internal delay? Advancing Science by Design Carl Grace 71 ENGINEERING DIVISION Solution: Clock Domain Crossing Analog Digital ADC CALCORE {MSB,LSB}

D D Q 0 D Q Q Correction Logic Data Buffer Output Data CLK/CLKB 1 CLKB/CLK PHI{1,2} EDGE_SELECT Solution: ADC bits are resampled and then handed off to core. In case of metastability, handoff can be phase offset 180 degrees Advancing Science by Design Carl Grace

72 ENGINEERING DIVISION Chip Configuration Cold ADC CONFIGURATION INTERFACE REGISTER FILE ADC0 w[0:15], w2[0:15] REGISTER FILE ADC1 w0[0:15], w2[0:15] External Interface Slow I/O REGISTER FILE CONFIG Config bits (128 8-bit registers) Memory-mapped configuration bits and calibration data Can be accessed using either I2C (preferred) or UART Advancing Science by Design

Carl Grace 73 ENGINEERING DIVISION Calibration Register File Write w0, w2 from Cal Engine or Config Logic WRITE BUS REG REG REG w0[0] w0[1] w0[n] CTRL w0[0:n] Register File Read w0, w2 REG

REG REG w2[0] w2[2] w2[n] w0[0:n] To Config Logic w2[0:n] w2[0:n] To Correction Logic Register File stores all calibration weights. Externally readable and writeable. Advancing Science by Design Carl Grace 74 ENGINEERING DIVISION Configuration Logic Memory Map Bit Contents

[7] Config Flag [6] Which ADC [5] Which Weight [4:1] Stage Address Address Range (Hex) Content FF-80 Configuration bits 7F-7E ADC1 Offset 7D-60 ADC1, W2 5F-5E ADC1 Gain

5D-40 ADC1, W0 3F-3E ADC0 Offset 3D-20 ADC0, W2 1F-1E ADC0 Gain 1D-00 ADC0, W0 [0] Which Byte Configuration bits fully defined in Smartsheet Advancing Science by Design Carl Grace 75 ENGINEERING DIVISION Nominal Reference Generator

Nominal reference generator. Each voltage and current highly programmable. Based on bandgap reference. (Bias currents for are included as well) Advancing Science by Design Carl Grace 76 ENGINEERING DIVISION 8-bit Reference DAC Each reference voltage implemented with an 8-bit DAC Highly flexible approach that allows a single DAC design to be used for all reference voltages Advancing Science by Design Carl Grace 77 ENGINEERING DIVISION Bandgap Reference Simulation Simulated performance looks great. However Advancing Science by Design Carl Grace

78 ENGINEERING DIVISION BJT Test LBNL had test BJT devices available from another tapeout (2011) Each test device is a 5x5 array of standard BJTs LBNL and BNL tested devices independently and correlated results Advancing Science by Design Carl Grace 79 ENGINEERING DIVISION BJT Measurements (77 K) LBNL Ie x Ve with VB=VC=0, 77K 1.00E+00 1.00E-02 Ie(A) 1.00E-04 1.00E-06 1.00E-08 1.00E-10 -0.2 1.00E-12 0

0.2 0.4 0.6 0.8 1 1.2 Ve(V) Measurements mostly agree, but simulation more than an order-ofmagnitude off! BNL Can use measured values to build a voltage reference, but we only measured a single device from one fabrication run done 7 years ago Design CMOS reference for backup Advancing Science by Design Carl Grace 80 ENGINEERING DIVISION Configurable Bias System VREFP_CMOS VREFN_CMOS VCMI_CMOS

VCMO_CMOS CMOS-Based Ref Gen VREFP_BJT VREFN_BJT VCMI_BJT VCMO_BJT BJT-Based Ref Gen VREFP_BUFF VREFN_BUFF VCMI_BUFF VCMO_BUFF optional external references pads optional external BGR Advancing Science by Design Carl Grace 81 ENGINEERING DIVISION CMOS Reference (current ref) Startup

VDDA TRIM<2:0> MP3 MP6-8 MP4 RPULLUP MP5 KICKSTART_B MP1 MN5 MP2 RDROP MN2 MN1 IREF Adjust reference current using trim and monitor output MN4 INT EXT

RBIAS RBIAS_EXT MN3 CMOS reference Advancing Science by Design Carl Grace 82 ENGINEERING DIVISION CMOS Reference (simulation) About 5% shift in bias current across temperature. Not amazing but good enough for Cold ADC. Advancing Science by Design Carl Grace 83 ENGINEERING DIVISION CMOS Reference (simulation) Bias Current Key Internal Node Key Internal Node Startup Circuit

Current Reference starts up fine in cold Advancing Science by Design Carl Grace 84 ENGINEERING DIVISION CMOS Reference (simulation) Bias Current Key Internal Node Kickstart to force current to flow Reference was started in zero-current-state. Kickstart successfully turned it on. Advancing Science by Design Carl Grace 85 ENGINEERING DIVISION High-Level Validation Super slow PEX simulation of 8-SHA array output Super fast VerilogAMS simulation

Verilog-AMS is a powerful tool for the full-chip simulation and validation of complex mixed-signal ASICs Advancing Science by Design Carl Grace 86 ENGINEERING DIVISION High-Level Validation This plot shows the calibration engine converging the correct gain values for each stage. In this simulation, ADC is schematic level (NOT a model). Verilog RTL for calibration engine and correction logic were imported into analog design environment. Not very impressive to look at, but it was a big milestone. Advancing Science by Design Carl Grace 87 ENGINEERING DIVISION Testing Draft of high-level test plan exists. Testing will go through three phases 1. 2. 3. Functionality Does the chip work? Evaluation Given that it works, how well does it work?

Optimization What is the optimum configuration and what are the optimal settings for the chip? What are the power/performance trades? Currently formulating detailed list of tests (including configuration settings) needed to validate design. Each lab will test in parallel, initially focusing on the blocks they own (each lab has cryogenic testing capability) BNL will attempt testing with FEMB as early as practical. Advancing Science by Design Carl Grace 88 ENGINEERING DIVISION 88 Testing Plan is for an August 22, 2018 tapeout Prototypes available in late Nov. 2018 Initial functionality and evaluation done in late Jan. 2019 FEMB integration and testing can begin earlier (integration can begin as soon as chip package is finalized and testing can begin as soon as basic chip functionality is established) ASIC optimization can be done in parallel with system tests, and new suggested configurations can be communicated to system test teams as they become available Advancing Science by Design Carl Grace 89 ENGINEERING DIVISION

89 Conclusion Cold ADC is coming together. High-level blocks mostly validated. Full verification is on-going and interfaces will need verification and possible debug. Still to do: 1. 2. 3. 4. 5. 6. Interface verification and debug Digital place-and-route Placement and routing of large analog macros Connection of macros to pads Metal fill / antenna / etc Full-chip simulation On track for a summer tapeout. Advancing Science by Design Carl Grace 90 ENGINEERING DIVISION 90 Contributors to Cold ADC ASIC Designers

Advisors BNL Mietek Dabrowski Yuan Mei Emerson Vernon Gabriella Carini Hucheng Chen FNAL Davide Braga Jim Huff Sandeep Miryala David Christian Grzegorz Deputch Marco Verzocchi

LBNL Dario Gnani Carl Grace Tarun Prakash Heather Richardson Dan Dwyer Cheng-Ju Lin Kam-Bui Luk Advancing Science by Design Carl Grace 91 ENGINEERING DIVISION 91 UNIVERSITY OF CALIFORNIA Advancing Science by Design ENGINEERING DIVISION

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